The present invention relates to a fast counter, and more particularly to a counter liable to count input pulses and to provide an output pulse each time an integer power of 2 of these pulses or integer power of 2 of these pulses plus half a pulse has been counted.
It will be noted that such a counter is particularly useful in constructing a programmable divider of the swallower counter type. However, the present invention has other applications which will appear to those skilled in the art.
A typical programmable divider of the swallower counter type is shown in FIG. 1.
In order to initially clarify the vocabulary, it will be noted that a counter up to a certain value N of which only the Nth counting value is extracted is equivalent to a divider by N. Indeed, it provides an output pulse every N input pulses. This is why the words divider and counter will be in certain cases indifferently used.
As it is shown in FIG. 1, a swallower counter comprises a divider 10 liable to divide by 2.sup.m or by 2.sup.m +1 subject to the state of a control signal arriving at its input 11. The output of the counter 10 is sent in parallel to first and second counters 12, 13. Counter 12 counts pulses up to a value B and counter 13 counts pulses up to a value A greater than B. Counter 13 is connected to count cyclically, i.e. the counting starts from zero once the maximum value A is attained. Counter 12 stops counting when the maximum value B is attained, until it is reinitialized by the output signal of counter 13. The output of counter 12 is applied to the input 11 of divider 10. Counters 12 and 13 are generally intended to have their counting values B and A programmed by a control signal sent for example on a bus (not represented), in a conventional way.
A swallower counter of the type shown in FIG. 1 enables, as a function of the choice of the values A and B, to achieve a frequency division by any chosen value non multiple of 2. The input frequency applied to the divider 10 is designated F0 and the output frequency of counter 13 is designated F2. If it is desired to have F2=F0/k, one can write: EQU k=A2.sup.m +B, EQU or EQU k=(A-B)2.sup.m +B(2.sup.m +1).
The circuit of FIG. 1 does provide F2=F0/k. Indeed, if it is considered that counter 10 is initially conditioned to divide by 2.sup.m +1, a pulse will be obtained at the output of counter 10 every 2.sup.m +1 periods of F0 and counter 12 will provide an output at 11 when B(2.sup.m +1) pulses of F0 arrive. Then, counter 12 is inhibited and divider 10 divides by 2.sup.m. Counter 13 has already counted B pulses. When the next A-B pulses are obtained at the output of divider 10, a pulse is provided at the output of counter 13 and the desired division factor k is indeed obtained.
It will be noted that only divider 10 counts rapidly, counters 12 and 13 counting substantially at a frequency 2.sup.m times smaller than this counter. In order to count pulses F0 following each other very rapidly, it is hence necessary to provide a fastest possible divider 10. If the operation of a counter or a divider is globally examined, it must achieve a sequence of logical operations between two successive transitions of a clock signal. The boolean arithmetic teaches that every complex logic operation such as counting can be decomposed in at most two levels of elementary logic operations corresponding to two switchings of a flip-flop. For a divider by a value other than an integer power of 2, an additional flip-flop switching time must be furthermore provided in order to store the output of the divider or an intermediate information in a latch. Thus, a conventional optimized counter, other than a divider by 2.sup.q, and especially a programmable divider, generally needs, between two pulses to count, sufficient time for three flip-flop switchings. In a given integrated circuit manufacturing technology, the elementary switching time of a flip-flop is predetermined and the maximum counting frequency hence encounters a fundamental limitation (which is for example of the order of 40 MHz in MOS technology, 2 micrometers, with a static type logic).
An object of the present invention is to provide a counter/divider other than by 2.sup.q comprising no fundamental limitation corresponding to a plurality of the above mentioned flip-flop switching times, and more particularly such a counter whose operating speed limit is as fast as that of a divider by 2.sup.q.
Another object of the present invention is to provide such a counter/divider liable, as a function of a control signal, to achieve a division by an integer power of 2 or by a power of 2 plus half a unity and to pass from one division mode to the other without reducing the counting speed limit.
Another object of the present invention is to provide a fast counter/divider usable in a swallower counter circuit.